The present invention relates generally to electronic design automation for integrated circuit (IC) designs, and, more particularly, to a method for automatically modifying IC layout.
IC layout is the representation of an integrated circuit in terms of planar geometric shapes that correspond to shapes actually drawn on photo-masks used in semiconductor device fabrication. IC layout may be created by automatic EDA tools, such as place and route tools or schematic driven layout tools, or created and edited by an IC designer manually by means of IC layout editors.
Complex IC chip designs are often based on libraries of many standard cells, provided by foundries or special intellectual property (IP) vendors. Layout of the individual standard cells is often handcrafted. But a standard cell provider may face many different requirements from different customers. Some require high-density, others may require high speed. Different customers may require different cell heights to fit in their specific layout structure. Besides, processes even within the same generation may slightly vary for different applications, which may create different device models and require different channel width ratios between a P-type metal-oxide-semiconductor (PMOS) and a N-type metal-oxide-semiconductor (NMOS), or P/N ratios, for short.
The traditional way of meeting different requirements by a standard cell vendor is to manually modify each standard cell layout. But given a large number of standard cells, plus numerous targets by various customers. Manual modification is very costly and time consuming.
Another way of meeting different requirements by a standard cell vendor is to use a commercial migration tool. However, commercial migration tools are more generic and mainly targeted at migration from one process generation to another. They are very complicated to operate, and require many computing hours. If every standard cell has to run through the migration tool for every different customer requirements, then any time or manpower saving from the migration tool will diminish. These generic migration tools will alter layout architecture, and enlarge cell areas that should all be avoided.
As such, what is needed is a method for automatically modifying the IC layout to meet specific requirements, such as cell heights and P/N ratio, within a process generation.